Long term memory storage for computer systems may take the form of a flash electrically erasable programmable read only memory (EEPROM) array. Flash EEPROM memory is an array of floating gate transistors arranged as memory cells in typical row and column fashion with circuitry for accessing individual cells. The transistors of the memory cells may be set to various charge states representing data stored at the memory cell. These cells furthermore retain the set charge state even after power is removed from the array, i.e., they are stable and adaptable to long term memory applications.
The array may further be arranged with physical pairing of the blocks or sub-blocks thereof, where the paired block or sub-block is on another part of the silicon chip. The pair blocks create a logical array in which even bits/bytes/words of data are stored on respective ones of the paired blocks. The odd/even blocks may be separately read/written and erased via a corresponding controller.
The cells are erased by applying a voltage to the cells. Because of the arrangement of the array, the erase operation affects the cells of an entire block of the array. Moreover, the erase operation typically proceeds with erasing a block, i.e., a corresponding odd/even sub-block pair containing the data to be erased, the erase process being implemented by the corresponding odd/even controller, respectively, for the odd/even sub-block pair.
A typical erase operation consists of applying the voltage pulse to the block to erase the cells of the block, verifying the erase has taken place, and moving on to the next block to be erased. All of the wordlines—odd and even—are erased together. That is, they are controlled together and erased together. Because of some process artifacts, the odd and even rows may not be equivalent causing one of them, either the odd or even, to erase faster or slower then the other. That is odd/even blocks may erase faster than the corresponding even/odd blocks resulting in an offset.